In digital circuits, there are frequent needs to interface between asynchronous systems. Asynchronous systems operate at different clocks that have no frequency or phase relationship to one another. The common design method used to pass an asynchronous signal into a system is to sample that signal with a flip-flop running at the system clock. The signal after the flip-flop is synchronous to the system clock. The following are but a few of the many patents in this area. U.S. Pat. Nos. 3,976,949; 4,070,630; 4,873,703; 5,070,443; 5,099,140; 5,256,912; 5,291,529; 5,418,825; 5,487,092, all of which are incorporated by reference herein.
The difficulty arises when one tries to synchronize a set of signals, a data vector. Because of metastability, which can occur when the asynchronous signal transitions close to the system clock and thus violate the set up or hold time of the flip-flop, all the flip-flops that are synchronizing the data vector cannot be guaranteed to resolve, or settle, to the correct value at the same time. Thus, not all the data bits in the vector can be sampled correctly by the system clock and the data vector can have the wrong value.
Conventional technique of "double-clocking" using two flip-flops works only for one bit value. In an n-bit vector, not all the bits will settle out of metastable state at the same time to propagate synchronously to the system clock.
Using Gray coding technique to encode the data vector into Gray codes (only one bit can transition in one time period) requires extra circuitry for encoding and decoding. For large data vector the encoding and decoding can be large and can become a time critical path in the system. Also, this technique only works if the values of the data vector change in sequential order. If the data vector can change value arbitrarily Gray coding cannot insure a single bit transition.
Other esoteric designs rely on delay elements or special cells that are dependent on the silicon process and technology of the synchronization circuitry.
The data vector synchronizer described herein has the following features:
Synchronizes an n-bit data vector from one clock domain to another. PA1 Assumes no relationship between the phase or frequency of the two clocks. PA1 Insures data integrity with minimal lost in time. PA1 Utilizes conventional synchronous digital logic with no delay or asynchronous elements.
Application
Moving data vectors in one clock domain to another. Especially suited for bus interface applications where one clock domain is totally asynchronous to another.
Synchronous FIFO buffering asynchronous data streams. Especially effective when used to synchronize the FIFO pointers across the clock domain to provide word counts or space counts inside the FIFO.